The static random access memory (SRAM) cell generally includes a first inverter, a second inverter, a first pass transistor and a second pass transistor. The first and the second inverters are cross-coupled to form a bistable latch circuit. The first pass transistor is coupled between the first inverter and a first bit line. The second pass transistor is coupled between the second inverter and a second bit line. In order to set or reset the bistable latch circuit, the first and the second pass transistors are enabled by driving a word line and accessed by driving the first and the second bit lines. Each of the first and the second inverters includes a respective p-type metal oxide semiconductor (PMOS) pull-up or load transistor, a respective n-type MOS (NMOS) pull-down or driver transistor, and a respective storage node between the respective PMOS pull-up transistor and the respective NMOS pull-down transistor.
When the SRAM cell has a static noise margin (SNM) near zero, it may have a weak write property, and thus may inadvertently flip its state. The SNM is a measure of the logic circuit's tolerance to noise in either of the states, i.e. by how much does the input voltage change without disturbing the present logic state. In other words, the SNM represents a measure of cell robustness.
When the size of the SRAM cell is scaled down, the SRAM cell has the huge device mismatch due to the process variation. A write operation to the SRAM cell is enabled by asserting a desired bit value on the first bit line and a complement of that value on the second bit line, and asserting the word line. A reduced static noise margin (SNM) can lead to cell upsets during a read operation or to unaccessed memory cells during the write operation. When the SRAM cell is powered by an extremely low supply voltage, it suffers a serious write failure due to the huge device mismatch.